This invention relates to the detection of communication errors across a chip boundary, particularly in the context of effecting communication of serial data across the chip boundary.
European Patent Application Publication No. 0840217, hereby incorporated by reference, describes an integrated circuit which uses a test access port controller (TAP controller) for effecting communication of serial data across the chip boundary. The TAP controller has two modes of operation. In a first mode of operation, test data is supplied to the chip via an input pin and resultant data following the test is supplied off chip via an output pin of the TAP controller. This operates according to the IEEE Standard 1149.1-1990, hereby incorporated by reference. In a second mode of operation, the TAP controller is used for the communication of a serial sequence of bits including data bits and flow control bits which represent data generated by functional circuitry on the chip, for example a processor.
To this end, the integrated circuit has a connection port comprising a serial data input pin and a serial data output pin. That connection port can be used to connect the integrated circuit to a cable, the remote end of which is connectable to an interface having circuitry for receiving the sequence of serial bits and for converting them into data for transmission to an off chip processing system connected to the interface. The interface also includes means for converting data received from the off chip processing system into a serial format suitable for transmission via the cable and connection port to the integrated circuit.
In a situation where the off chip processing system has an independent power supply to the integrated circuit, it is quite possible that power can become disconnected from the integrated circuit while the interface and off chip processing system remain xe2x80x9cpowered upxe2x80x9d. In this scenario it is important that communication between the integrated circuit and the interface is prevented to prevent garbage data being transmitted and received.
Another fault that can arise is that the cable becomes physically disconnected from the connection port of the integrated circuit. In that context also it is important to prevent functional circuitry on the integrated circuit from attempting to transmit data off chip or attempting to analyze data received on-chip.
The present invention obviates or at least mitigates these disadvantages.
According to one aspect of the present invention there is provided an integrated circuit including a connection port having a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, and a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins. The test access port controller is connected to the test logic in a first mode of operation to effect communication of serial test data under control of an incoming clock signal, and operable in a second mode of operation to communication data as a sequence of serial bits according to a predetermined protocol between the connection port and the on-chip functional circuitry.
The integrated circuit includes error detection circuitry for detecting an error condition in the protocol and gating circuitry responsive to detection of the error condition to prevent communication of subsequent data until the error condition is detected as having been removed.
The integrated circuit can also include a data adaptor which is connectable to the input and output pins via the test access port controller in the second mode of operation, wherein in the second mode the data adaptor is supplied with parallel data and control signals from said on-chip functional circuitry and converts said parallel data and control signals into the sequence of serial bits including flow control bits and data bits for communicating off chip via the test access port controller under the control of the incoming clock signal. The data adaptor receives from off chip via the serial data input pin a sequence of serial bits including flow control bits and data bits for conversion into parallel data and control signals for said on-chip functional circuitry.
In a preferred embodiment, according to said predetermined protocol a stop bit is transmitted after each predetermined number of serial data bits, the error condition being detected by detecting lack of said stop bit.
Preferably, an error signal is asserted by the error detection circuitry on detection of the error condition. That error signal can be used to generate a visible indication to a user than an error condition has been detected.
The integrated circuit can additionally comprise circuitry for detection of removal of the error condition. This can be used to re-establish communication of serial data.
In one embodiment, the connection port includes a pull-up resistor which generates a logical value having a predetermined state indicating an error condition when a physical connection is broken at the connection port.
Embodiments of the invention also provide a communication system including an integrated circuit as herein defined above wherein the connection port is connected to a cable in the normal state, and an interface device having an interface port connected to a remote end of the cable and operable to receive and transmit data between the interface and the integrated circuit according to said predetermined protocol, said interface being operable to convert said data into a format suitable for communication to a network via an Ethernet connection.
The data adaptor in a preferred embodiment has first and second ports for receiving and transmitting respectively parallel data and control signals between the data adaptor and the functional circuitry.
The data adaptor preferably includes circuitry for generating flow control information from the flow control bits and the data to be transferred between the functional circuitry and the data adaptor. The flow control information can be one of the following types:
1) forward flow control information generated from flow control bits in the incoming sequence of serial bits and output by at least one pin of the first port;
2) forward data control information which is generated by the on-chip functional circuitry in association with the parallel data signal supplied to the first port;
3) reverse data control information which is generated from data bits in the sequence of serial bits received by the data adaptor; and
4) reverse flow control information which is generated by the on-chip functional circuitry in response to parallel data received thereby.
The forward flow control information can additionally be generated in dependence on the status of a storage circuit in the data adaptor which temporarily holds data and control signals pending their conversion into serial bits.
In the described embodiment, the parallel data signals received and transmitted by the data adaptor are eight bits wide.
The integrated circuits can include various source/destination logic on-chip. In one embodiment, the integrated circuit includes an on-chip bus system to which is connected a message converter which converts requests received from the bus system into parallel data for supply to the data adaptor, and converts parallel data received from the data adaptor into requests for supply via the bus system. The on-chip functional circuitry can comprise at least one processor connected to the bus system. The bus system can include at least one memory bus effecting communications with on-chip or off-chip memory connected or connectable to that memory bus.